Virtual Memory
Table of Contents
1. Virtual Memory
Computers need to run a lot of processes. If each process was given its own address space on a 64-bit computer, your RAM will quickly run out of space.
Most processes don’t use all their address space: they mostly use one block of memory in the code segment, another block in the stack, and maybe a few blocks in the heap/data segments. However, we still want to give processes the illusion that they own the entire contiguous segment of memory.
The solution is virtual memory: to chop up main memory into pages of a few KiB each, then only store the pages the process actually tries to access. Virtual memory is responsible for given each process the illusion it has access to the entire address space, then translating that to the actual pages located in physical memory.
We can think of our computer as having two address spaces: the virtual address space is the set of addresses the program knows about, and the physical address space is the set of addresses that map to actual physical locations in memory. For each process, the memory manager then translates between these two spaces.
1.1. Paged Memory
Memory is paged, which means memory addresses can be split into two parts: the page number, and an offset. Memory translation translates virtual page numbers (VPN) to physical page numbers (PPN). Offsets within the same page are the same across virtual memory and physical memory.
1.2. Page Table
A page table is a lookup table used to translate virtual addresses to physicsal addreses for a given process. Each entry in the table corresponds to a virtual page number, and if that page is in memory, the entry has a corresponding physical page number. Otherwise, the entry should tell the OS to trigger page fault or to load page from disk.
Each page table entry also stores various status bits, which include a valid bit, a dirty bit, and a write protection bit. The valid bit indicates if the page is in memory (DRAM) or only on disk. The dirty bit tracks if the virtual memory was changed, and uses write-back to write to disk. Finally, the write protection bit tracks if that page should never be modified.
Page tabes are stored in main memory. To minimize performance penalties, we transfer cache lines instead of individual words between DRAM and a processor cache. We can also use a cache for frequently used page table entries. This cache is called the translation lookaside buffer (TLB), which tracks VPN-PPN mappings. The TLB is much closer to the CPU and predates data caches (hence the older name).