RISC-V Assembly

To ensure functions in RISC-V behave properly, we use a calling convention to ensure that registers are used properly. Each register has a name associated with them. They signal the most common use case for that register:

The stack pointer tracks the end of the stack. Everything above the stack pointer (higher memory addresses) is reserved, whereas everything below is unallocated. Everything between sp and the original location of sp is useable space for your program. To use the stack, move sp down, and store data in the new space. After freeing the space, sp should moved back up.

The return address stores where a function should return back to after completing. A function will assume that ra is where to jump back to when returning.

The argument registers are used to store function arguments. a0 and a1 are also used for return values. These can be changed by functions, so we can’t assume they are unchanged after a function call.

The temporary registers are used for intermediate calculations. These can also be changed by functions.

The saved registers are used for permanent variables. They cannot be changed by functions. If a function changes a saved register, it is responsible for restoring the old value before returning.

Use the add instruction for addition:

add x1 x2 x3   # x1 = x2 + x3

Use the sub instruction for subtraction:

sub x1 x2 x3   # x1 = x2 - x3

These are all the arithmetic operations supported by RISC-V:

add rd rs1 rs2    # add
sub rd rs1 rs2    # subtract
and rd rs1 rs2    # bitwise and
or rd rs1 rs2     # bitwise or
xor rd rs1 rs2    # bitwise xor
sll rd rs1 rs2    # shift left logical
srl rd rs1 rs2    # shift right logical
sra rd rs1 rs2    # shift right airthmetic
slt rd rs1 rs2    # set less than (signed): rd = (rs1 < rs2) ? 1 : 0
sltu rd rs1 rs2   # set less than (unsigned)

Immediates are numerical constants. For example, to add an immediate to a register, use the special instruction addi:

addi x3 x4 10   # x3 = x4 + 10

Note that both addi x3 x4 x5 and add x3 x4 10 are both invalid RISC-V instructions: be careful with using the register versus the immediate version of an instruction. An immediate subtraction instruction does not exist because we can subtract an immediate by using its negative version. Therefore, addi is a signed instruction.

Additionally, since the number zero appears very often in code, the register x0 is “hard-wired” to the value 0.

There are two main representation schemes used: unsigned numbers, and two’s complement for signed numbers.

For unsigned numbers, we fill the unused top bits with zeros (zero-extension).

For signed numbers, we fill the unused top bits with the most significant bit (sign-extension).

In RISC-V, every control flow operation tries to move to a specified instruction in memory. Labels identify a specific instruction in code so we can reference it with a control flow operation. The following are all of the RISC-V control flow operations:

beq rs1 rs2 label    # branch if equal: if rs1 == rs2, jump to label
bne rs2 rs2 label    # branch if not equal
blt rs1 rs2 label    # branch if less than (signed)
bge rs1 rs2 label    # branch if greater or equal (signed)
bltu rs1 rs2 label   # branch if less than (unsigned)
bgeu rs1 rs2 label   # branch if greater or equal (unsigned)
j label              # jump to label unconditionally

We can use the jal (jump and link) and the jr (jump register) instructions to create functions:

jal rd label         # jump and link: jumps to label, sets rd to pc+4 (next instruction)
jr rs1               # jump register: jump to instruction at address rs1

When registers are not enough to store our data, we may need to use main memory instead. Here, we can use these instructions:

lw rd imm(rs1)       # load word: load 4 bytes from memory at imm+rs1 into rd
sw rs2 imm(rs1)      # store word: store the 4 bytes in rs2 into memory at imm+rs1
lb rd imm(rs1)       # load byte (signed, sign extend the byte)
lbu rd imm(rs1)      # load byte (unsigned, zero extend the byte)
sb rs2 imm(rs1)      # store byte (LSB only)

Remember since we use little-endian, the LSB is stored in the lower memory address. Additionally, when we store a byte, we take the LSB from the register.

A pseudoinstruction is an instruction that does not exist as a hardware instruction, but is composed of one or more actual hardware instructions that is translated automatically by the assembler. Pseudoinstructions exist to make certain operations easier:

li rs1 1       # load immediate: loads the immediate value 1 to rs1
la rd label    # load address: loads the address of the label
mv rd rs1      # move: copies the value in rs1 into rd
not rd rs      # flips all the bits in rs

The R-type (register-type) is designed for instructions with 3 registers and no imemdiates (e.g. add, sub). Each register is identified by its number: 32 registers, so we need 5 bits to identify each register.

The opcode identifies the specific instruction in use. It is always the last 7 bits of the instruction across all formats, so we can use this to determine which format is in use. However, some similar instructions get assigned the same opcode (e.g. all arithmetic R-type instructions). In these cases, funct3 and funct7 are used to further differentiate instructions with the same opcode.

The I-type (immediate-type) is designed for instructions with 2 registers (rs1 and rd) and 1 immediate. Note that stores use rs1 and rs2 (no destination register rd), so they use a different type. Notice that the immediate is only allocated 12 types, which means they can only hold values between -2048 and 2047.

The S-type (store-type) is designed for store instructions, where you have 2 source registers and an immediate.

U-type (upper immediate) instructions are for lui and auipc:

lui rd imm        # load upper immediate: rd = imm << 12
auipc rd imm      # add upper immediate to program counter: rd = (imm << 12) + PC

These are primarily used in the li and la pseudoinstructions. Since addi only accepts a 12-bit immediate, we need a way to load immediates larger than 12 bits: li uses lui to accomplish this under the hood.

For auipc, often when we write code, we want to allow multiple programs to be combined. However, each time we do this, it would change the absolute positions of our labels. Therefore, many instructions involving labels use relative addressing with auipc.

Labels don’t actually exist at the machine level, so the assembler actually converts the labels into explicit references to a particular line of code. It does this by calculating an offset, which specifies how many bytes off we would need to jump to get to that label.

Note that these offsets will always be at least a multiple of 2 (since RISC-V core instructions are all 32-bit, and some extensions use 16-bit). Thus, we don’t actually need to store the last 0 in the binary representation.

Branch instructions use the B-type (branch-type) format:

Note that branch instructions have 13-bit immediates, which gives us \([-4096, 4094]\) bytes of offset, which is \(2^10\) instructions up and down.

J-type (jump-type) instructions are for the jump instruction jal:

As with the B-type, the last 0 bit is not stored. Jumps have 21-bit immediates, so we have a range of up to \(2^18\) instructions up and down.